This invention relates to a method for preparing a silicon substrate with a transparent quartz film on its surface having improved electrical insulation and thus suited for use in optical waveguide devices for optical communication.
Quartz substrates and silicon substrates are common substrates for use in optical waveguide devices for optical communication. The silicon substrates are typically used in the manufacture of semiconductor integrated circuits and characterized by a good heat conductivity and surface amenability to a variety of processes including etching, oxidation and deposition. They are available in large size and at a low cost.
In order to utilize quartz substrates and silicon substrates as the waveguide device substrate, a quartz glass thin film must be formed on the quartz or silicon substrate. Processes for forming such a thin film include CVD, evaporation, flame deposition, sol-gel, and high pressure oxidation processes.
More particularly, a first quartz film, known as an under clad, is formed on a quartz or silicon substrate to a thickness of about 10 to 20 xcexcm. On the under clad, a second quartz film having a higher refractive index is deposited to a thickness of about 5 to 10 xcexcm. This second quartz film is designated a core. A pattern through which light enters the core is formed as by etching. Finally, a third quartz film having a lower refractive index than the core is deposited thereon. The third film is designated an over clad. The stack of these three quartz films constructs an optical waveguide for an optical branching or switching device, that is, a quartz base optical waveguide.
Currently, terrace or platform substrates are often used. These substrates are prepared by applying an alkali such as a potassium hydroxide aqueous solution to a silicon substrate for anisotropic etching to form a step of at least 5 xcexcm on the substrate surface. An oxide film having a greater thickness than the step is formed on the substrate surface by a CVD or flame deposition technique. The oxide film is polished away until the silicon surface is exposed.
This method is described in JP-A 63-131104. Referring to FIG. 2, a series of steps are illustrated. First, as shown in FIGS. 2-1 and 2-2, a silicon substrate 1 is wet etched to form a step 2, yielding a silicon substrate 1xe2x80x2 having a stepped or recessed surface consisting of higher and lower surface regions. On the stepped surface (one side), a quartz film 3 (buffer layer) is formed as shown in FIG. 2-3, by a flame deposition technique. Then, the entire quartz film 3 is polished away until the silicon on the higher surface region is exposed as shown in FIG. 2-4.
This method suffers from several problem. On one side of the silicon substrate 1xe2x80x2 having a stepped surface resulting from anisotropic etching, the quartz film 3 is formed by the flame deposition technique which involves heat treatment above 1,000xc2x0 C. Then, the substrate can warp outward of the quartz film side to a warpage of about 200 xcexcm as shown in FIG. 2-3xe2x80x2. Such a large warpage cannot be fully offset simply by placing a weight on the substrate. During the step of polishing away the deposited film, a vacuum chuck must be used to correct the warpage. The warpage must be offset within the range of xc2x11 xcexcm over the entire wafer, which requires a very cumbersome operation.
If a quartz film is directly formed on a recessed surface of a silicon substrate 1xe2x80x2 as shown in FIG. 2-4xe2x80x2, thermal stresses are applied near the corner of the recess due to differential thermal expansion between the substrate and the film during sintering. A potential remains for creating micro-cracks 4 near the corner.
In addition to the above-described problem associated with polishing, another problem arises from the flame deposition technique. Upon formation of a quartz film, it must be doped with boron oxide and phosphorus oxide. This, in turn, requires to control the concentration of dopants and the concentration distribution in plane and depth directions, which can otherwise adversely affect the electrical properties (insulation and dielectric constant) of the quartz film.
An object of the invention is to provide a method for preparing a silicon substrate having on its surface a quartz film with improved electrical insulation and free of micro-cracks, the substrate being suited for use in optical devices, typically optical waveguide devices.
According to the invention, a silicon substrate having a step of at least 5 xcexcm high on one surface is furnished. The silicon substrate is subjected to high pressure heat oxidation to form thereon an oxide film which is thinner than the height of the step. Then the oxide film on the higher surface region is removed until the silicon surface is exposed in the higher surface region.
More particularly, a silicon substrate having a step on one surface, that is, higher and lower surface regions connected by a step on the same side is subjected to high pressure heat oxidation whereby the silicon substrate is provided with a terrace structure. Opposite surfaces of the silicon substrate are oxidized under a pressure higher than the atmospheric pressure whereupon a dense, pure oxide film (quartz film) is formed on each surface of the substrate. The oxide film provides improved electrical insulation. Since the oxide films are formed on opposite surfaces of the substrate, the substrate as oxidized is unlikely to warp, and the potential for creating micro-cracks in the oxide film is minimized. Since the oxide film is thinner than the step, the silicon layer can be exposed simply by polishing away the oxide film on the higher surface region. The polishing step takes only a short time. The silicon substrate produced by the method of the invention is a terrace substrate having improved electrical properties, high quality and minimized warpage, which is advantageously used as optical waveguide devices in optical integrated circuits.
The method of the invention is successful in briefly producing a silicon substrate having improved properties through simple steps.